This invention relates in general to digital computer systems and in particular to digital data communication between microprocessors and a peripheral device.
In a computer system, information exchange between its various components are usually effected by means of a common bus. For example, a microprocessor, a memory, a Direct Memory Access device (DMA), and peripheral devices are all connected to the same system bus. Information flow between these components are controlled by a set of control lines which are also carried along the system bus. Generally the control lines serve two functions: one is to specify what type of bus operation is to be performed; the other is to provide timing information to synchronize the transfer operation. Each microprocessor family has its own specific bus interface protocol which is generally different from ones belonging to other families.
However, for most common bus operations, the protocols fall within one of two forms. For data read or write operations, one form of bus interface protocol has the read strobe (RD*) dedicated to reading data, and the write strobe (WR*) dedicated to writing data. The symbol "*" used as a part of the name of a signal in this application indicates that the signal is active low. The alternate form has the timing information for both the read and write operations carried by the data strobe (DS*). The single DS* signal is used in conjunction with the read/write status signal (R/W*) to transfer data in either direction. Prior art bus interfaces are usually designed to cooperate with only one form of bus interface protocol, not both.
When it is necessary for the peripheral device to notify the processor of a transmit or receive operation the peripheral intends to perform, the peripheral sends an interrupt signal to the processor. The processor then sends an interrupt (transmit or receive) acknowledge signal to the peripheral to inform the peripheral that it may begin the intended operation.
Similarly, commonly used bus interface protocols transmit interrupt acknowledge signals also in two alternate forms. One form is the status interrupt acknowledge signal (SITACK*) which merely flags that an interrupt acknowledge cycle is in progress, with the timing information being carried in either RD* or DS*. The alternate form is the interrupt acknowledge strobe signal (PITACK* in short for pulse interrupt acknowledge) which is a strobe that both flags interrupt acknowledge as well as carries the timing information about the cycle.
Also some microprocessors have separate address and data buses but others employ a single multiplexed address/data bus. The multiplexed data bus must be used in conjunction with an address strobe signal (AS*) which is present to latch the address on the address/data bus as well as chip select and channel select information.
Apart from the different ways of implementing the control lines and the timing signals, different microprocessors also may have different timing considerations. For example, some may have the data strobe available early before the data is ready for latching. Others may have the data ready for latching early, with the strobe available later.
With the various incompatible interface requirements of different processors such as those described above, conventional peripheral devices are typically optimized for interface to one particular processor, so that extra efforts and expense may be required for interfacing to other types of processors. When more than one processor interface must be supported either a bonding option or a function select pin is typically used. Both of these approaches require additional logic which compromises speed and flexibility and translates to interfaces which are optimized for no processor.
In prior bus interface protocols, a bus interface is only required to derive a strobe signal from few signals. Thus where the bus interface protocol calls for separate read strobe and write strobe signals as well as interrupt transmit acknowledge and interrupt receive acknowledge signals, a NAND-gate may be used to derive the strobe signal with the four signals enumerated above as inputs to the gate. Since only one of the four signals will be active at any one time a NAND-gate is adequate for deriving the strobe signal. Where the bus interface is required to be compatible with a number of bus interface protocols, the number of inputs to the NAND-gate will be increased to more than four. This requires connecting lines between the gate and interface signal pins on the bus interface spread over a distance on the interface chip. Extra drivers or buffers may be required in order to adequately drive the signals across such distances. Such extra logic causes considerable delay in deriving the strobe signals for operating the peripheral device.
Since the internal strobe signal of the peripheral device is derived from any one of the many possible input control line options, these inputs can be OR'ed together to give the single internal strobe. In terms of negative true logic, a multi-input NAND gate may be used.
Since the NAND gate will have a large number of inputs connected to interface input pins which are spread far apart, the implementation of a NAND gate would normally be impractical also because of size considerations in addition to the delay caused. For example, a two or three input NAND-gate constructed in CMOS would normally have linear dimensions of the order of 20 microns per gate. Increasing the number of inputs to the gate would, of course, increase gate size. If the size of the gate is increased, the gate will have higher capacitance which slows down its operation. Consequently, the size of the gate will have to be increased further to increase its speed. Thus, a brute force extension of the same gate to an 8-input one, as illustrated in FIG. lA, would result in each gate having linear dimensions of the order of 1,000 microns. Such gate will not only occupy a large area, but also consume much power. Alternatively, as shown in FIG. lB, it is possible to combine several 2- or 3-input NAND gates together to form an equivalent 8-input NAND gate. However, such configuration would result in the signal having to propagate through three levels of primitive gates resulting in considerable time delay.
Referring to FIG. 1C, another factor for delay due to propagation through a conventional NAND gate is that the variously distributed inputs will have to cover considerable distance to reach the NAND gate which is normally localized inside the chip. This requires substantial drive power from the input buffers. Typically, the input buffers are made up of a level shifter and an inverter, and external interface requirement places an upper limit on the size of these input buffers. In order to drive the signal over a considerable distance into the chip, additional drivers are required. Thus, it is likely that the input signal will have to propagate through four primitive gates to reach the NAND gate itself. If the NAND gate is cascaded into three levels, the input signal will have to go through a total of seven primitive gates.
Accordingly, it is a primary object of the invention to provide a universal bus interface which contains all the signal pins necessary to interface to any one of several different processors, without compromising their performances and without external logic nor options beyond tying of unused signals.
It is another object of the invention to provide an implementation of the NAND-gate which is highly efficient and has minimum delay.